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Small Delay Tracing Defect Testing

Authors

Lakshmaiah Alluri1 and Hemant Jeevan Magadum2, 1HDG, CDAC, India, 2ITNS, CDAC, India

Abstract

This Small Delay Tracing Defect Testing detect small delay defects by creating internal signal races. The races are created by launching transitions along simultaneous two paths, a reference path and a test path. The arrival times of the transitions on a ‘convergence’ or common gate determine the result of the race. On the output of the convergence gate, a static hazard created by a small delay defect presence on the test path which is directed to the input of a scan-latch. A glitch detector is added to the scan latch which records the presence or absence of the glitch.

Keywords

Delay, Defect, detector, glitch, testing.

Full Text  Volume 11, Number 21