Peiyi Zhao1, William Cortes1, Congyi Zhu2 and Tom Springer1, 1Chapman University, USA, 2Nangjing University, China
Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior stateof-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.
Dynamic power, low supply voltage, flip-flop.