Praveen Pilla and Vinaya Gudeangadi, Intel Technology India Pvt. Ltd

At the SoC level, channels are used to interconnect different IPs. When the number of wires passing through the channels is too high, the area occupied by these channels becomes a substantial portion of the total SoC area. The problem with channels is that they only carry signals, making them an inefficient way to utilize design area. To optimize area, IPs are often abutted at the SoC level, and channels are replaced by SoC feedthrough wires that run across the IPs. In SoC designs where IPs are abutted, it is common practice to route feedthrough wires across the IPs to reduce the area dedicated to channels. In an abutted design methodology, the two IPs connected to each other may not be adjacent due to floorplan constraints. This is why SoC feedthrough wires are routed across intermediate IPs. Modern design planning tools can handle the creation of SoC feedthroughs at the IP level. However, in the case of Multiple Instantiated Blocks (MIBs i.e., multiple instances of the same reference), these tools struggle to handle them efficiently and effectively. This paper discusses various scenarios where design tools fail to manage SoC feedthrough creation and proposes solutions to address these challenges.

MIB: Multiple Instantiated blocks, SoC: System on Chip, IP: Intellectual Property, WNS: Worst negative slack, FEP: Failing Endpoints, TNS: Total negative slack.